IPX-AES: AES Symmetric Security Range
General Description
The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination of several functions and operating modes for a very small FPGA footprint.
The family of IPX-AES IP-Cores is an encryptor / decryptor core range that efficiently implements in FPGA the Advanced Encryption Standard as specified in the Federal Information Processing publication FIPS-197 of the National Institute of Standards and Technology.
The IPX-AES module can be customized to ensure its optimization for a wide range of specific application fields with a design architecture that can be adapted to support from low up to very high bit-rates. Its flexibility allows combining several functions and operating modes on very small footprints.
Technical Description
Functions
With addressing keys of 128, the IPX-AES cores execute decryption or encryption.
Data-stream handling
The IPX-AES cores can handle the data and secret keys in two different ways. The single stream option consists of a core capable of managing data with a single key, before a new update of this key. The multiple stream option is a feature capable of managing multiple ciphering processes together, each based on a different secret key.
Chaining modes
The inter-data-block chaining supports all existing modes that can be used separately or combined into a single design: ECB (Electronic Code-Book), CBC (Cipher Block Chaining), CTR (Counter). Other modes could be supported.
Data busses
The incoming, outgoing and key data are handled on either common or separate buses. Data bus width is 128 bits wide.
Clock
The processes use a single clock and can be reset asynchronously.
Features
| OPTIONS |
IPX-AES-MD | IPX-AES-M | IPX-AES-H | |
| Functions | Encryptor | - |  |
|
| Decryptor | |
- | - | |
| Throughput bit rate | 2,5 Gbps | |
|
|
| 3,7 Gbps | - | |
|
|
| 15 Gbps | - | - | |
|
| Data-stream handling | Single Stream | |
|
|
| Up to 16 streams | |
- | - | |
| Operation modes | ECB | |
|
|
| CBC | |
- | - | |
| CTR | - | |
|
|
| AES Data and Key Bus widths | 128 bits | |
|
|
Key Features
- Multiple stream management
-
Renewable security
Applications
- Digital Cinema (DCI),
- Secure Content applications in Broadcast, Post-production, Archiving, Video Surveillance, Medical Imaging.
- Digital Right Management (DRM)
Resources
Available for the most recent Altera & Xilinx FPGAs. Resources details provided on request.
|
IPX-AES-MD |
Virtex-5 |
| Slices | 800 |
| RAMBs | 4 |
| Work Frequency | 220Mhz |
| Encryption/decryption cycle count | 11 Clock Cycles |
| Decryption throughput | 2,5 Gbit/s |
| Key update cycle count | 66 cycles |
|
IPX-AES-M |
Virtex-5 |
| Slices | 500 |
| RAMBs | 0 |
| Work Frequency | 320Mhz |
| Encryption/decryption cycle count | 11 Clock Cycles |
| Encryption throughput | 3,7 Gbit/s |
| Key update cycle count | On the fly |
|
IPX-AES-H |
Virtex-5 |
| Slices | 2000 |
| RAMBs | 0 |
| Work Frequency | 320Mhz |
| Encryption/decryption cycle count | 11 Clock Cycles |
| Encryption throughput | 15 Gbit/s |
| Key update cycle count | On the fly |
Example : A Digital Cinema Application
These three version of the IPX-AES are designed specifically to meet Digital Cinema needs, and demonstrate how efficient the IPX-AES can be.
The modules specified are designed for Xilinx FPGAs and comply with the Digital Cinema Initiative requirement Specification V1.2.
The IPX-AES-MD Multi-Assets Decryptor can manage multiple assets together (video, audio and subtitles) without AES core updates. This core is also capable of bypassing the decryption process for non-encrypted data. the IPX-AES-M-2K and IPX-AES-H-4K Link Encryptors or the IPX-AES-H-4K-Link-Encryptor can be used to re-encrypt the uncompressed data between the mediablock and the projector.
