IPX-DDR : Memory Controllers IP by intoPIX

General Description

In order to offer the most compact and complete solutions to customers, intoPIX proposes memory controller IP-Cores that have been especially designed to ease the integration of our JPEG 2000 encoders and decoders into FPGA platform, speeding up time-to-market. High video processing pipelines requires high performance access to external memory. intoPIX has developed a strong expertise to deliver memory controllers interfaces for DDR2/DDR3/DDR4/LPDDR2/LPDDR3.

By completing your JPEG 2000 solutions with our controller IP-Cores, you will benefit from intoPIX’s knowhow in IP-Core integration. 

Key Features

Flexible Architecture

Optimized FPGA footprint and performance per configurations. 

The IPX-DDR cores are adapted according to the image compression and processing pipeline .

Easy J2K integration

  The cores are optimal to be used with intoPIX JPEG2000 Encoder & Decoder IP-cores 
    

Silicon proven

The intoPIX DDR cores have been validated in many applications, including Digital Cinema, Broadcast,, ProAV, GIS, Machine Vision, Defense, ...

Various IPs 

 The cores can target either Xilinx or Intel FPGAs . They are highly customizable and configurable to manage the sharing with multiple JPEG2000 IP-core, the sharing with other processing (ie other codecs, FEC, Video buffering,...), etc.

    

Resources

Resources for Intel or Xilinx FPGA  can be provided on request depending on your specific configuration.