IP-cores for FPGA & ASIC

TicoRAW is the new RAW !

intoPIX TicoRAW is a revolutionary RAW (Bayer) image processing and compression technology, extremely tiny and low power.

intoPIX has developped various architectures running at different pixel per clock to target a wide range of pixel rates/ frame rates/ image sensors resolutions and a wide range of FPGA devices & ASIC technology nodes. Encoding or Decoding can be achieved into the small AMD-Xilinx & Intel FPGAs, robust for real-time operation with no latency. intoPIX offers silicon-proven IP with very low gate count & SRAM consumption in ASICs.

With such a rapid evolution of available images, image sensors and video resolutions, the need for new ways to handle RAW / image sensor data is bigger than ever before.

With TicoRAW, you can capture, transmit, store, edit, preserve, analyze,.. RAW Bayer data "more efficiently" with small bandwidth and file sizes, preserving the full flexibility of "RAW".

Learn more about TicoRAW

IP-cores Features

TicoRAW IP-cores are fully available and silicon-proven for FPGA and ASIC designs

Image / Video	Color space: RAW (CFA-BAYER) - RGGB, RCCB, etc. optional Monochrome/Greyscale and 4:2:2* modes Bit Depth: 8, 10, 12, 14, 16 Resolutions: Any (2Mpx to 160Mpx or more (see example for, HD, 2K, 4K, 8K, 10K hereunder) Pixel Rate / frame rate*: Any (depending on intoPIX IP-core configuration & targeted device)
TicoRAW Processing & Compression (Latency, Quality, Rate Control)	(Sub) intra-frame : down to 0.1 millisecond Real-time operation guaranteed (no overflow or underflow) Fixed latency - Only few lines of pixels (number of lines depends on the profile) Adjustable compression ratio down to 1 bit per pixel Support for lossy / visually lossless / near-lossless / mathematically. lossless CBR (Constant Bit Rate) operation (optional : Constant Quality mode) ISP proxy output within decoder (Decoder IP-core Addon)
FPGA/ASIC Implementation	Various Pixel Per Clock architectures available to achieve the minimal footprint into the chip. Low-cost implementation in any FPGAs: very low FPGA logic and internal RAM usage (No external DDR required) Fit in Xilinx (AMD) Spartan-6, Artix-7, Kintex-7, Kintex Ultrascale, Zynq, Virtex Ultrascale, UltrascalePlus, Versal Fit in Intel Cyclone V, Arria V, Stratix V, Cyclone 10, Arria 10, Stratix 10, Agilex Fit in Lattice Low Gate Area (low gate count / low memory) for ASIC - Silicon Proven Encoder and decoder have approximately the same complexity IP-core customizable per application

* in 422 , the frame rate will be the half of the frame rate achieved in RAW Bayer mode

NEW - HD, 4K, 8K, 10K, 16K, 20K RAW ...
and your configuration for FPGA & ASIC

Based on all the features we are supporting, it is possible to provide custom versions to address your specific needs.

Contact us for your own configuration.

See hereunder a list of typical configurations. The Max fps will depend on the selected encoder /decoder and its related pixel-per clock architecture.

IP-CORES -ENC / -DEC	Color sampling	Sensor Bit depth	Resolutions examples	Max fps at 100 MHz*	Max fps at 250 MHz*	Max fps at 300 MHz*	Max fps at 1 GHz*
IPX-TicoRAW-2K (up to 2048-pixels width)	RAW CFA Bayer	8, 10, 12, 14, 16	2048 x 1080 2048 x 2048	670 354	839 442	1006 530	3354 1769
IPX-TicoRAW-4K (up to 4096-pixels width)	RAW CFA Bayer	8, 10, 12, 14, 16	4096 x 2160 4096 x 4096	168 88	209 110	250 132	837 441
IPX-TicoRAW-8K (up to 8192-pixels width)	RAW CFA Bayer	8, 10, 12, 14, 16	8192 x 4320 8192 x 8192	44 22	105 55	124 68	418 220
... ASK FOR YOUR CONFIGURATION

* Max Frequency (MHz) of the IP-cores can be adjusted according to your selected pixel-per-clock architecture, and your targeted FPGA or ASIC technology node