IPX-DDR: Memory Controller IPs by intoPIX

General Description

In order to offer a dense and integrated solution, intoPIX proposes flexible memory controller IP-Cores - such as the IPX-DDRx - and IPX-MLB, designed to ease the integration of the intoPIX JPEG 2000 encoders and decoders into an FPGA platform, speeding up time-to-market. 

High video processing pipelines require high performance access to external memory. intoPIX has developed a strong expertise to deliver memory controller interfaces for DDR2/DDR3/DDR4/LPDDR2/LPDDR3.

By completing your JPEG 2000 solutions with our controller IP-Cores, you will benefit from intoPIX’s knowhow in IP-Core integration. 



Key Features

Flexible Architecture

Optimized FPGA footprint and performance per configurations. 

The IPX-DDR cores are adapted according to the image compression and processing pipeline

Easy J2K integration

The cores are optimal to be used with intoPIX JPEG2000 Encoder & Decoder IP-cores achieving high bandwidth efficiency and supporting small burst.
    

Silicon proven

The intoPIX DDR cores have been validated in many applications, including Digital Cinema, Broadcast,, ProAV, GIS, Machine Vision, Defense, ...

Multi Ports IP 

Highly customizable and configurable IPX-DDR to manage the sharing with multiple JPEG 2000 IP-cores and the sharing with other processing ( other codecs, FEC, video buffering) through standard interfaces (AXI or Avalon) using the IPX-MLB.