IP-cores for FPGA & ASIC

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​JPEG XS compression IP-cores for HD, 4K and 8K
​At the speed of light!

intoPIX has developed various optimized TICO-XS architectures running a different pixel per clock to target a wide range of resolutions and a wide range of FPGA devices & ASIC technology nodes. 

TICO-XS is a revolutionary compression technology, standardized at JPEG, extremely tiny in FPGA & ASIC. It fits into the smallest Xilinx & Intel devices, it is robust for real-time operation with no latency. It offers a very low gate count & SRAM consumption in ASICs.

​IP-cores Features

 Image/Video Features
  •  Color space: Any (RGB, YCbCr, YUV, XYZ)
  • Color Sampling: 4:0:0 (monochrome, Alpha); 4:2:0*, 4:2:2, 4:4:4 and 4:2:2:4*
  • Bit Depth: 8, 10, 12, 14, 16
  • Interlaced & Progressive frame
  • Resolutions: Any (SD, HD, 2K, 4K, 8K)
  • Frame Rates: Any (depending on intoPIX IP-core configuration & targeted device). 
    • For Real-time video and High speed video
TICO-XS  Compression
(Latency, Quality, Rate Control)
  • (Sub) intra-frame
  • JPEG XS compliant (and beyond) (ISO/IEC 21122-1)
  • Real-time operation guaranteed (no overflow or underflow) 
  • Fixed latency - Only few lines of pixels (number of lines depends on the profile)
  • Adjustable compression rate for lossy / visually lossless (down to 1.5 bpp**) / near-lossless / math. lossless 
  • Full transparency to uncompressed down to 3 bits per pixel (bpp)
  • HDR (&SDR) support
  • intoPIX "Feature" Release profile
  • CBR (constant bit rate) operation - Adjustabe down to 36:1 (1bpp)
  • Optional Add-On: embedded x1 (1/4) and x2  (1/16) downscaler / proxy in decoder
  • Optional intoPIX "Flawless Imaging Processing" Addon for KVM, AVoIP, PC applications. See TICO-XS² solutions
FPGA/ASIC Implementation
  •  Low-cost implementation in any FPGAs: very low FPGA logic and internal RAM usage (No external DDR required)
    • Running in the smallest Xilinx Spartan-6, Spartan-7 Artix-7, Kintex-7 and Ultrascale , Ultrascale Plus, Zynq
    • Running in the smallest Intel Cyclone V, Arria V, Stratix V, Cyclone 10, Arria 10, Stratix 10
  • Low Gate Area (low gate count / low memory) for ASIC
  • Encoder and decoder have approximately the same complexity 
  • IP-core size, performance, video resolution & max frame per second - customizable per application*
  • Various pixel per clock architectures

* via 4:2:2 plus alpha channel

**Depending on type of content and resolutions.


​NEW configurations for FPGA & ASIC 

Based on all the features we are supporting, it is possible to provide custom versions to address your specific needs. 

Contact us for your own configuration. 


See hereunder a list of typical configurations:

IP-CORES EXAMPLES
-ENC  / -DEC
 Max* res
 Max* fps Color sampling Bit depth
 Minimum frequency
IPX-TICO-XS-HD-60-422 1920x1080 60 4:2:28, 10, 1245 MHz
IPX-TICO-XS-HD-60-444 1920x1080 60 4:4:4 / 4:2:2 8, 10, 1260  MHz
 IPX-TICO-XS-HD-240-444 NEW! 1920x1080 240 4:4:4 / 4:2:2 8, 10, 12 240 MHz
 IPX-TICO-XS-HD-480-444 NEW! 1920x1080 480 4:4:4 / 4:2:2 8, 10, 12 240 MHZ
 IPX-TICO-XS-4K-30-444  4096x2160 304:4:4 / 4:2:2  8, 10, 12 120 Mhz
 IPX-TICO-XS-4K-60-422 4096x2160 60 4:2:2 8, 10, 12150 MHz
 IPX-TICO-XS-4K-60-444 4096x2160 604:4:4 / 4:2:2 8, 10, 12 240 MHz
 IPX-TICO-XS-4K-120-422 4096x2160 120 4:2:2 8, 10, 12 300 MHz
IPX-TICO-XS-4K-120-444 4096x2160 120 4:4:4 / 4:2:2 8, 10, 12 240MHz
 IPX-TICO-XS-8K-60-422 NEW! 7680x4320 60 4:2:2 8, 10, 12 150 MHz
IPX-TICO-XS-8K-60-444 NEW! 7680x4320** 60 4:4:4 / 4:2:2 8, 10, 12 240 MHz
IPX-TICO-XS-8K-120-422 NEW!
 7680x4320 120 4:2:2 8,10, 12 300 MHz

* "Max" means it supports any standard video resolutions and frame rates below.
**8192x4320 on request

What our users say 

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