TICO-XS by intoPIX
"We invented the ultimate codec to manage and transmit more pixels with lower power, low bandwidth and lossless quality at the speed of light"
Engineered by intoPIX, TICO-XS is an evolution of TICO RDD35 offering more compression capabilities
with an extremely small footprint in ASIC and FPGA and fast performances on CPU & GPU
intoPIX has made significant intellectual property development in lightweight low latency video compression, from inventing and standardizing the world’s smallest and fastest mezzanine compression technology TICO (SMPTE RDD35) supported by the TICO Alliance, to being the proponent and co-developer of creating the world first international ISO standard technology "JPEG XS", addressing this matter.
The technology and associated products are covered by one or more claims of patent, awarding intoPIX's hard work and innovation. The new TICO-XS will gather momentum during this year.
Due to increasing resolutions (4K/8K), higher frame rates, 360° capture and higher quality pixels (e.g. HDR), all devices and infrastructures have to handle ever increasing data volumes. Whether virtual reality, gaming, live production, automotive or digital cinema workflows, the JPEG XS mezzanine codec standard can be applied wherever uncompressed video is currently used.
As a lightweight image coding system, it also offers line based latency with compression ratios from 2:1 to 12:1 (or even more) while maintaining lossless quality.
JPEG XS is the first ISO standard (ISO/IEC 21112) designed for latency-critical applications offering lossless quality at low complexity.
- Low power consumption (through lightweight processing)
- Ultra low latency in coding and decoding
- Lossless picture quality
- Small size on chip
- Fast on software (CPU with the use of SIMD and GPU)
WITHOUT SIGNIFICANT INCREASE IN REQUIRED BANDWIDTH & COST
- Low power consumption (through reasonable bandwidth interfaces)
- Longer cable runs
- Perfect fit for existing and new infrastructures
- More pixels at a reduced cost
(higher resolutions, higher frame rates, higher bit depth)
When uncompressed is not realistic
TICO-XS is the solution
Live IP production
Studio over IP
AV over IP
Pro-AV over IP
Video wall management
Displays & devices
Connectivity & interfaces
VR / AR
Wearables / HMDs
Wired / wireless
5G & IoT
Cloud processing & storage
Interfaces & connectivity
Support higher data streams (HD, 4K, 8K, …) in existing systems and infrastructures using the available pipeline bandwidth.
Enable the use of a lower link rate for applications where high link rates may not be possible.
Increase the number of streams or the stream resolution that could be supported in a multi-stream configuration.
Reduce the number of lanes in a display or sensor interface needed to transport a stream in order to save power, cost, or both.
Significantly reduce the internal video bandwidth (and power consumption) in systems such as mobile devices, cameras, video servers and displays.
Increase the storage, video buffer or frame buffer capacity with cost-effectiveness for applications where high link rates may not be possible.
Typical operating bitrates
|Formats||Bitrates||IP network & SDI mapping|
|HD 720p60 / HD 1080i60||70 - 200 Mbps||1 to X streams over 1GbE|
|HD 1080p60||125 - 400 Mbps||1 to X streams over 1GbE|
|4K 2160p60||500 Mbps - 1,6 Gbps||1 stream over 1GbE|
1 to X streams over 10GbE
Single 3G-SDI / single HD-SDI
|8K 4320p60||2 - 6.4 Gbps|| 1 to 4 streams over 10GbE|
Single 3G-SDI / single 6G-SDI / single 12G-SDI
|IMAGE||Color format||RGB, YCbCr|
|Color subsampling||4:0:0, 4:2:2, 4:4:4|
| Bit depth||8 / 10 / 12 / 16 bits per component|
|Resolution||Any up to 8192 x 4096 pixels|
|Frame rates||Any (depending in IP-core or FastTICO SDK configuration)|
|PROCESSING||Compliance||JPEG XS standard (ISO/IEC 21122-1 - coming profiles) for TICO-XS|
| Quality|| Full transparency to uncompressed down to 3 bits per pixel (bpp)|
Visually lossless down to 1bpp*
|Rate control||Constant bit rate operation (CBR) - adjustable down to 36:1 (1bpp)|
|Latency||(Sub-) intra frame: line-based latency (microseconds)|
|Proxy mode||Embedded downscaler in decoder available (decode 1/4 or 1/16 proxies)|
*according to ISO flicker test and depending on type of content
Evaluation & implementations
From Q2 2019
- small footprint
- ultra-low memory
- low power (no external DDR)
- various configurations
- Xilinx & Intel FPGA
- ASIC like TSMC 12, 16, 28, 40nm
From Q2 2019
(First) IP-core releases
ENCODER - DECODER
|Max. res||Max. fps||Color sampling||Bit depth||ASIC|
|IPX-TICO-XS-HD-60-444-12-Enc or -Dec||1920 x 1080||60||4:2:2, 4:4:4||8, 10, 12||✓||✓||✓|
|IPX-TICO-XS-UHD4K-60-444-12-Enc or -Dec||4096 x 2160||60||4:2:2, 4:4:4||8, 10, 12||✓||✓||✓|
Discover our TICO XS IP-core and SDK implementations (coming soon!)
- Various HD/4K/8K implementations and products are available today based on TICO SMPTE RDD35
- Many more TICO-XS IP-cores & SDKs will be released this year, including the new ISO/IEC 21112 JPEG-XS profiles, and new performance capabilities for FPGA, ASIC, CPU & GPU:
Tell us more about your needs
Xilinx FPGA & SoCs IPs
Spartan, Artix, Zynq, Kintex & Virtex
Intel FPGA & SoCs IPs
Cyclone, Arria & Stratix
Intel x86 CPU