• THE LIGHTWEIGHT LOW LATENCY CODEC  

    An extremely small codec in hardware (FPGA / ASIC),  highly parallelizable in software (CPU / GPU), preserving full quality 

    Discover our implementations here

TICO by intoPIX

TICO is a disruptive, innovative, visually lossless, light-weight and line-based compression specifically designed to be used instead of uncompressed video in many applications. This revolutionary technology is extremely tiny in FPGA or ASIC, fast and powerful in CPU or GPU, and robust for real-time operation with no latency.

Up to now, image and video were sent or stored uncompressed within many electronic devices and infrastructures (display, camera, mobile, servers, recorders, ...) . 

TICO is a smart upgrade path to manage higher resolutions (4K, 8K, …) and frame rates while assuring visual quality, keeping power and bandwidth at a reasonable budget and significantly reducing the complexity and cost of a system, a chip or an infrastructure.

TICO is easy to integrate. Code, hardware IP-cores and software libraries are licensable from intoPIX. The technology and associated products are covered by one or more claims of patents awarding intoPIX's hard work and innovation.

Key Features

Zero Latency

Few microseconds – very few lines of pixels 
(selectable from 1 to x)

Lossless Quality

Visually Lossless up to 4:1

 Robust over multiple coding generations

Low Power, tiny

Silicon-proven & easy to implement into low cost FPGA or ASIC designs Low gate count, low memory usage

Mobile to 4K/8K
​SDR & HDR

Compatible with different resolutions, from mobile to 4K/8K UHDTV, via multiple usual transport schemes. Signaling of HDR included

Parallelizable

Highly parallelizable, Real-time or faster than real-time in CPU and GPU

Interoperable

Submitted to SMPTE as SMPTE RDD35 with the the support of the 50+ TICO Alliance members


When uncompressed is not realistic 

TICO is the solution ! 

Support higher Data Streams (HD, 4K, 8K …) in existing systems and infrastructures using the available pipeline bandwidth.

Enable the use of a lower link rate for applications where high link rates may not be possible.

Increase the number of streams or the stream resolution that could be supported in a multi-stream configuration.

Reduce the number of lanes in a display or sensor interface needed to transport a stream in order to save power, cost, or both.

Significantly reduce the internal video bandwidth (and power consumption) in systems such as mobile devices, cameras, video servers and displays.

Increase the storage, video buffer or frame buffer capacity with cost-effectiveness for applications where high link rates may not be possible.

Discover our TICO IP-cores and FastTICO SDKs 

CUSTOM ASIC

ASIC IPs

Tell us more about your needs

Xilinx FPGA & SoCs IPs

Spartan, Artix, Zynq, Kintex & Virtex

Intel FPGA & SoCs IPs

Cyclone, Arria & Stratix 

SDK

FastTICO

Intel x86 CPU

 Nvidia, AMD, Intel GPU